;********************************************************************************
; @module IO-W65C22
; @type utility
; @device Western Design - W65C22N Versatile Interface Adapter
; @details
;********************************************************************************

.ifndef INCLUDE_IOW65C22
INCLUDE_IOW65C22 = 1

; IO-CHIPS OFFSETS FOR PINS FROM BASE ADDRESS
IO_RB   = $0  ; Register B (ORB/IRB)
IO_RA   = $1  ; Register A (ORA/IRA)
IO_DDRB = $2  ; Data Direction Register B
IO_DDRA = $3  ; Data Direction Register A
IO_T1CL = $4  ; Timer 1 Counter Low/High
IO_T1CH = $5
IO_T1LL = $6  ; Timer 1 Latch Low/High
IO_T1LH = $7
IO_T2CL = $8  ; Timer 2 Counter Low/High
IO_T2CH = $9
IO_SR   = $a  ; Shift Register
IO_ACR  = $b  ; Auxiliary Control Register
    ; ACR Masks
    IO_ACR_MASK_PA          = %00000001  ; 
    IO_ACR_MASK_PB          = %00000010  ; 
    IO_ACR_MASK_SR          = %00011100  ; 
    IO_ACR_MASK_T2          = %00100000  ; 
    IO_ACR_MASK_T1          = %11000000  ; 
    ; SR Modes
    IO_ACR_SR_DISABLE       = %00000000  ; Disabled
    IO_ACR_SR_SIN_T2        = %00000100  ; Shift in under control of T2
    IO_ACR_SR_SIN_PHI2      = %00001000  ; Shift in under control of PHI2
    IO_ACR_SR_SIN_PHIE      = %00001100  ; Shift in under control of external clock
    IO_ACR_SR_SOUT_FREE_T2  = %00010000  ; Shift out free running at T2 rate
    IO_ACR_SR_SOUT_T2       = %00010100  ; Shift out under control of T2
    IO_ACR_SR_SOUT_PHI2     = %00011000  ; Shift out under control of PHI2
    IO_ACR_SR_SOUT_PHIE     = %00011100  ; Shift out under control of external clock
    ; T1 Modes
    IO_ACR_T1_IRQ_LOAD      = %00000000  ; Timed interrupt each time T1 is loaded
    IO_ACR_T1_IRQ_CONT      = %01000000  ; Continuous interrupts
    IO_ACR_T1_IRQ_LOAD_PB7  = %10000000  ; Timed interrupt each time T1 is loaded - PB7 One Shot output
    IO_ACR_T1_IRQ_CONT_PB7  = %11000000  ; Continuous interrupts - PB7 Square wave output
IO_PCR  = $c  ; Peripheral Control Register
    ; PCR Masks
    IO_PCR_MASK_CA1         = %00000001  ; 
    IO_PCR_MASK_CA2         = %00001110  ; 
    IO_PCR_MASK_CB1         = %00010000  ; 
    IO_PCR_MASK_CB2         = %11100000  ; 
    ; CA1 Modes
    IO_PCR_CA1_IN_AE        = %00000000   ; Input-negative active edge
    IO_PCR_CA1_IP_AE        = %00000001   ; Input-positive active edge
    ; CA2 Modes
    IO_PCR_CA2_IN_AE        = %00000000  ; Input-negative active edge
    IO_PCR_CA2_IN_AE_IRQ_IND= %00000010  ; Independent interrupt input-negative edge
    IO_PCR_CA2_IP_AE        = %00000100  ; Input-positive active edge
    IO_PCR_CA2_IP_AE_IRQ_IND= %00000110  ; Independent interrupt input-positive edge
    IO_PCR_CA2_IN_HANDSHAKE = %00001000  ; Handshake output
    IO_PCR_CA2_IN_PULSE_OUT = %00001010  ; Pulse output
    IO_PCR_CA2_IN_LOW_OUT   = %00001100  ; Low output
    IO_PCR_CA2_IN_HIGH_OUT  = %00001110  ; High output
    ; CB1 Modes
    IO_PCR_CB1_IN_AE        = %00000000   ; Input-negative active edge
    IO_PCR_CB1_IP_AE        = %00010000   ; Input-positive active edge
    ; CB2 Modes
    IO_PCR_CB2_IN_AE        = %00000000  ; Input-negative active edge
    IO_PCR_CB2_IN_AE_IRQ_IND= %00100000  ; Independent interrupt input-negative edge
    IO_PCR_CB2_IP_AE        = %01000000  ; Input-positive active edge
    IO_PCR_CB2_IP_AE_IRQ_IND= %01100000  ; Independent interrupt input-positive edge
    IO_PCR_CB2_IN_HANDSHAKE = %10000000  ; Handshake output
    IO_PCR_CB2_IN_PULSE_OUT = %10100000  ; Pulse output
    IO_PCR_CB2_IN_LOW_OUT   = %11000000  ; Low output
    IO_PCR_CB2_IN_HIGH_OUT  = %11100000  ; High output

IO_IFR  = $d  ; Interrupt Flag Register
    ; IFR bits
    IO_IFR_CA2  = 0
    IO_IFR_CA1  = 1
    IO_IFR_SR   = 2
    IO_IFR_CB2  = 3
    IO_IFR_CB1  = 4
    IO_IFR_T2   = 5
    IO_IFR_T1   = 6
    IO_IFR_IRQ  = 7
IO_IER  = $e  ; Interrupt Enable Register
IO_RANH = $f  ; no handshake

    ; TODO: leave?
    ; .struct VIA_Pins
    ;     RB   .byte   ; $0
    ;     RA   .byte   ; $1
    ;     DDRB .byte   ; $2
    ;     DDRA .byte   ; $3
    ;     T1CL .byte   ; $4
    ;     T1CH .byte   ; $5
    ;     T1LL .byte   ; $6
    ;     T1LH .byte   ; $7
    ;     T2CL .byte   ; $8
    ;     T2CH .byte   ; $9
    ;     SR   .byte   ; $a
    ;     ACR  .byte   ; $b
    ;     PCR  .byte   ; $c
    ;     IFR  .byte   ; $d
    ;     IER  .byte   ; $e
    ;     RANH .byte   ; $f  ; no handshake
    ; .endstruct
.endif