use other shift mode instead of generating clk pulse

This commit is contained in:
matthias@arch 2024-01-09 02:28:54 +01:00
parent 326b2f6247
commit e61871ed0f

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@ -293,18 +293,20 @@ scancode_handler: .res 2 ; pointer to a function that handles new scancod
_DisableClock
; set shift register to output
; shift out the startbit = data low
; set SR to shift out with PHI2 and shift out zeros
lda ps2kb::VIA + IO::ACR
and #<~IO::ACR_MASK::SR
ora #IO::ACR::SR_SOUT_PHIE
ora #IO::ACR::SR_SOUT_PHI2
sta ps2kb::VIA + IO::ACR
stz ps2kb::VIA + IO::SR
; shift out the startbit = data low
_EnableClock
_DisableClock
; reset shift register to start the count at 0 again
lda #IO::ACR::SR_SOUT_PHIE
trb ps2kb::VIA + IO::ACR
tsb ps2kb::VIA + IO::ACR
and #<~IO::ACR_MASK::SR
sta ps2kb::VIA + IO::ACR
; set SR to shift out with external clock
ora #IO::ACR::SR_SOUT_PHIE
sta ps2kb::VIA + IO::ACR
; setup the low timer byte
lda #<ps2kb::TIMER_SEND