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;;********************************************************************************
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;; @module keyboard
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;; @type drive
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;; @details:
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;; Support for a PS2 Keyboard using the shift register of a 6522 VIA
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;; Pressing a key causes 11 bits to be sent: 1 start - 8 keycode - 1 parity - 1 stop
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;; The VIA is set up to interrupt after 8 bits have been shifted into the shift register
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;; from the external clock pulses of the keyboard (additional hardware required to
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;; address the hardware bug of the VIA, where bit get lost when the external clock
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;; transition happens during falling edge of PHI2). After reading the shift register,
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;; the VIAs T2 timer is set to interrupt after the last 3 bits have been shifted in,
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;; which takes about ~230ms.
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;;********************************************************************************
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.ifndef INCLUDE_KEYBOARD
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INCLUDE_KEYBOARD = 1
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.include "system.h65"
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.scope kb
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Import kb,init,irq_shift_reg_handler,irq_timer_handler,keycode,key_read
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KB_IO = IO1
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.endscope
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.endif
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@ -1,106 +0,0 @@
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.include "keyboard.h65"
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.include "string.h65"
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.include "lcd.h65"
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Export kb,init,irq_shift_reg_handler,irq_timer_handler,keycode,key_read
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.bss
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key_read: .res 2
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keycode: .res 1
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.code
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;;********************************************************************************
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;; @function Initialize the PS2 keyboard
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;; @modifies: A
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;;********************************************************************************
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.proc init
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; - use the shift register interrupts to read the first 8 bits
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; set shift register to shift in under external clock on CB1
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; - configure timer for timing the read of the last 3 bits
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; timer 2 one shot mode is sufficient, leaves T1 available
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lda #(IO::ACR::SR_SIN_PHIE | IO::ACR::T2_IRQ_LOAD)
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tsb kb::KB_IO + IO::ACR
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; the 3 last bits take about 230us, at @1MHz => wait 230 cycles and then the shift register
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; (this could be shorter since the it takes a few cycles after the interrupt)
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lda #230
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sta kb::KB_IO + IO::T2CL
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stz key_read
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stz key_read+1
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; enable SR interrupts
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lda #(IO::IRQ::IRQ | IO::IRQ::SR)
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sta kb::KB_IO + IO::IER
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; load SR to reset
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lda kb::KB_IO + IO::SR
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rts
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.endproc
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;;********************************************************************************
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;; @function Read the first 8 bits an
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;; @modifies: A
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;; @details
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;; - read shift register
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;; - disable shift register interrupts
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;; - reset shift register
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;; - enable timer 2 interrupts
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;; - start timer 2
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;; IO::SR has to be read before the next bit is shifted in, which happens ~75us after the irq
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;; at 1MHz, handling this interrupt takes about 50us (without any additional debug code),
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;; so it should work
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;;********************************************************************************
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.proc irq_shift_reg_handler
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lda kb::KB_IO + IO::SR
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sta key_read
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stz kb::KB_IO + IO::SR
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; disable SR interrupts
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lda #IO::IRQ::SR
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sta kb::KB_IO + IO::IER
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; enable timer interrupts
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lda #(IO::IRQ::IRQ | IO::IRQ::T2)
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sta kb::KB_IO + IO::IER
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; start timer, low order count already in latch after init
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lda #1
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sta kb::KB_IO + IO::T2CH
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rts
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.endproc
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;;********************************************************************************
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;; @function Read the last 3 bits after after timer 2 is up
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;; @modifies: A
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;; @details
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;; - read shift register
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;; - disable timer 2 interrupts
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;; - enable shift register interrupts
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;; - reset shift register
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;;********************************************************************************
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.proc irq_timer_handler
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lda kb::KB_IO + IO::SR
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sta key_read + 1
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lda kb::KB_IO + IO::T2CL ; clear interrupt flag
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; disable timer interrupts
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lda #(IO::IRQ::T2)
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sta kb::KB_IO + IO::IER
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; enable shift register interrupts
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lda #(IO::IRQ::IRQ | IO::IRQ::SR)
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sta kb::KB_IO + IO::IER
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; reset SR
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stz kb::KB_IO + IO::SR
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; rotate bit 2 (last bit of keycode) into the carry
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lda key_read+1
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ror
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ror
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ror
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lda key_read ; not affecting carry
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rol ; rotate carry into byte, rotate startbit into carry
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; TODO byte is inverted, maybe consider wasting 256 bytes for a bit reverse lookup table?
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sta keycode
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stz key_read
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stz key_read+1
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rts
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.endproc
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