314 lines
9.3 KiB
Plaintext
314 lines
9.3 KiB
Plaintext
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.include "ps2_keyboard.h65"
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.include "string.h65"
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.include "lcd.h65"
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.include "parity.h65"
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Export ps2kb,init,begin_receive,send_command,scancode,status,scancode_handler
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Export ps2kb, _receive_irq_shift_reg_handler, _receive_irq_timer_handler
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.bss
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status: .res 1
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send_last_bits: .res 1
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send_data: .res 1
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send_cmd: .res 1
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key_read: .res 2
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scancode: .res 1
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scancode_handler: .res 2
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.code
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;;********************************************************************************
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;; @macro Enable the clock signal from the keyboard
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;; @modifies: A
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;; @details
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;; Stop pulling the keyboards clock low
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;;********************************************************************************
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.macro _EnableClock
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; set pin to input
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lda ps2kb::VIA + ps2kb::CLK_PULL_DDR
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and #<~ps2kb::CLK_PULL_MASK
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sta ps2kb::VIA + ps2kb::CLK_PULL_DDR
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.endmacro
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.macro _DisableTimerIRQ
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; set pin to input
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lda ps2kb::VIA + ps2kb::CLK_PULL_DDR
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and #<~ps2kb::CLK_PULL_MASK
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sta ps2kb::VIA + ps2kb::CLK_PULL_DDR
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.endmacro
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;;********************************************************************************
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;; @macro Disable the clock signal from the keyboard
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;; @modifies: A
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;; @details
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;; Pulls the keyboards clock low
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;;********************************************************************************
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.macro _DisableClock
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; set pin to output
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lda ps2kb::VIA + ps2kb::CLK_PULL_DDR
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ora #ps2kb::CLK_PULL_MASK
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sta ps2kb::VIA + ps2kb::CLK_PULL_DDR
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; set pin low
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lda ps2kb::VIA + ps2kb::CLK_PULL_R
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and #<~ps2kb::CLK_PULL_MASK
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sta ps2kb::VIA + ps2kb::CLK_PULL_R
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.endmacro
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.proc init
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stz key_read
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stz key_read+1
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stz scancode
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stz status
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; T2 oneshot mode, clear shift reg
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lda ps2kb::VIA + IO::ACR
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and #<~IO::ACR_MASK::SR
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ora #IO::ACR::T2_IRQ_LOAD
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sta ps2kb::VIA + IO::ACR
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; the 3 last bits take about 230us, at @1MHz => wait 230 cycles and then the shift register
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; (this could be shorter since the it takes a few cycles after the interrupt)
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lda #<ps2kb::TIMER
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sta ps2kb::VIA + IO::T2CL
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; load this rts as scancode_handler
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StoreDByte @rts, scancode_handler
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@rts:
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rts
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.endproc
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;;********************************************************************************
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;; @function Start receiving data from the keyboard
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;; @details
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;; - use the shift register interrupts to read the first 8 bits
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;; - configure timer for timing the read of the last 3 bits
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;; @modifies: A
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;;********************************************************************************
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.proc begin_receive
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; disable timer interrupts (this might be called while waiting on the last 3 bits)
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IO_DisableIRQ ps2kb::VIA, IO::IRQ::T2
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; set shift register to shift in under external clock on CB1
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lda ps2kb::VIA + IO::ACR
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and #<~IO::ACR_MASK::SR
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ora #IO::ACR::SR_SIN_PHIE
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sta ps2kb::VIA + IO::ACR
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stz key_read
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stz key_read+1
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stz scancode
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bit status
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; set to RECEIVE_KEYS only if RECEIVE_ANSWER is not set
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bvs @receive_answer
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lda #ps2kb::STATUS::RECEIVE_KEYS
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sta status
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@receive_answer:
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_EnableClock
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; todo setup irq handlers
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IO_EnableIRQ ps2kb::VIA, IO::IRQ::SR
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; reset and start SR
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stz ps2kb::VIA + IO::SR
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rts
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.endproc
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;;********************************************************************************
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;; @function Read the first 8 bits an
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;; @modifies: A
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;; @details
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;; - read shift register
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;; - disable shift register interrupts
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;; - reset shift register
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;; - enable timer 2 interrupts
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;; - start timer 2
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;; IO::SR has to be read before the next bit is shifted in, which happens ~75us after the irq
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;; at 1MHz, handling this interrupt takes about 50us (without any additional debug code),
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;; so it should work
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;;********************************************************************************
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.proc _receive_irq_shift_reg_handler
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lda ps2kb::VIA + IO::SR
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sta key_read
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stz ps2kb::VIA + IO::SR
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IO_DisableIRQ ps2kb::VIA, IO::IRQ::SR
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IO_EnableIRQ ps2kb::VIA, IO::IRQ::T2
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; start timer, low order count already in latch after init
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lda #>ps2kb::TIMER
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sta ps2kb::VIA + IO::T2CH
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rts
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.endproc
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;;********************************************************************************
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;; @function Read the last 3 bits after after timer 2 is up
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;; @modifies: A
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;; @details
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;; - read shift register
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;; - disable timer 2 interrupts
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;; - enable shift register interrupts
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;; - reset shift register
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;; - jump to the subroutine pointed to by scancode_handler
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;;********************************************************************************
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.proc _receive_irq_timer_handler
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lda ps2kb::VIA + IO::SR
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sta key_read + 1
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lda ps2kb::VIA + IO::T2CL ; clear interrupt flag
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IO_DisableIRQ ps2kb::VIA, IO::IRQ::T2
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; reset SR
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; disabling shifting in acr seems necessary to reset - otherwise
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; it continues counting and interrupts after the first 5 bits of the next keypress
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lda #(IO::ACR::SR_SIN_PHIE | IO::ACR::T2_IRQ_LOAD)
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trb ps2kb::VIA + IO::ACR
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tsb ps2kb::VIA + IO::ACR
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stz ps2kb::VIA + IO::SR
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IO_EnableIRQ ps2kb::VIA, IO::IRQ::SR
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lda key_read+1
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ror ; stop bit -> C
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sta key_read+1 ; parity in bit 0, D7 in bit 1
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ror ; parity -> C
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ror ; D7 -> C
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lda key_read ; not affecting carry
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rol ; C -> bit 0, startbit -> C
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Reverse A
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sta scancode
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CalculateOddParity
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eor key_read+1 ; if bit 0 is 1 - parity error
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and #1 ; bit 1 is still D7
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bne @parity_error
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; check what to do with the scancode
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bit status
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bcc @status_not_receive_keys
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jmp (scancode_handler)
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@status_not_receive_keys:
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bvc @status_ignore
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jmp _process_cmd_answer
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@status_ignore:
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rts
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@parity_error: ; TODO handle somehow
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lda #$ff
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sta scancode
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DEBUG_LED_ON 2
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rts
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.endproc
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;;********************************************************************************
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;; @function Send a command to the keyboard
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;; @modifies: A,X,Y
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;; @param A: The command byte
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;; @param X: The data byte or 0 if only the command byte should be sent
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;;********************************************************************************
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.proc send_command
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sta send_cmd ; store if it needs to be resent
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cpx #0
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beq @jmp_send_byte
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@store_data:
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stx send_data
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@jmp_send_byte:
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jmp _send_byte
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.endproc
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;;********************************************************************************
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;; @function Send a byte to the keyboard
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;; @modifies: A,X,Y
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;; @param A: The byte to send
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;; @details
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;; - pull clock low to stop keyboard transmissions
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;; - setup shift register to shift out
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;; - put startbit + D0-6 in shift register
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;; - store D7 + parity + stopbit in memory
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;; - TODO setup SR and T2 interrupt handlers
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;;********************************************************************************
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.proc _send_byte
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pha
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IO_DisableIRQ ps2kb::VIA, IO::IRQ::T2
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_DisableClock
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; (re)set shift register to shift out under external clock on CB1
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lda ps2kb::VIA + IO::ACR
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and #<~IO::ACR_MASK::SR
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ora #IO::ACR::SR_SOUT_PHIE
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sta ps2kb::VIA + IO::ACR
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IO_EnableIRQ ps2kb::VIA, IO::IRQ::SR
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pla
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pha
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; split into the 11 bits
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CalculateOddParity
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tax
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pla
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clc ; C = 0 (startbi)
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rol ; C -> bit 0, D7 -> C
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sta ps2kb::VIA + IO::SR
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txa
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ror ; C -> bit 0 (D7)
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ora #%00000100 ; set stopbit
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; A = 000001P7 where 7 = D7, P = Parity
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sta send_last_bits ; loaded into SR by irq handler
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; stop pulling clk low, which causes the startbit to be shifted out
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_EnableClock
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rts
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.endproc
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;;********************************************************************************
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;; @function Send the lasts 3 bits
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;; @modifies: A
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;; @details
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;; - load the remaining 3 bits of the transmission into the shift register
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;; - disable shift register interrupts
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;; - enable timer 2 interrupts
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;; - start timer 2
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;;********************************************************************************
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.proc _send_irq_shift_reg_handler
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lda send_last_bits
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sta ps2kb::VIA + IO::SR
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; disable SR interrupts
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lda #IO::IRQ::SR
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sta ps2kb::VIA + IO::IER
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; enable timer interrupts
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lda #(IO::IRQ::IRQ | IO::IRQ::T2)
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sta ps2kb::VIA + IO::IER
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; start timer, low order count already in latch after init
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lda #>ps2kb::TIMER
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sta ps2kb::VIA + IO::T2CH
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rts
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.endproc
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;;********************************************************************************
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;; @function Send databyte or reveice the keyboards answer
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;; @modifies: A, X, Y
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;; @details
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;; - disable timer 2 interrupts
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;; - if send_data is zero:
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;; - begin_receive
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;; - set status RECEIVE_ANSWER
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;; - else
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;; - send_byte send_data
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;; - set send_data = 0
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;;********************************************************************************
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.proc _send_irq_timer_handler
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lda ps2kb::VIA + IO::T2CL ; clear interrupt flag
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IO_DisableIRQ ps2kb::VIA, IO::IRQ::T2
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; no SR reset necessary, will be done in begin_receive or send_byte
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lda send_data
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beq @receive
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stz send_data
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jmp _send_byte
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rts
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@receive:
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lda #ps2kb::STATUS::RECEIVE_ANSWER
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sta status
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jmp begin_receive
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.endproc
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.proc _process_cmd_answer
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@success:
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rts
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.endproc
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