2023-10-26 19:51:20 +02:00
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;********************************************************************************
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; @module IO-W65C22
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; @type utility
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; @device Western Design - W65C22N Versatile Interface Adapter
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; @details
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;********************************************************************************
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.ifndef INCLUDE_IOW65C22
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INCLUDE_IOW65C22 = 1
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; IO-CHIPS OFFSETS FOR PINS FROM BASE ADDRESS
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2023-10-27 16:50:58 +02:00
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IO_RB = $0 ; Register B (ORB/IRB)
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IO_RA = $1 ; Register A (ORA/IRA)
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IO_DDRB = $2 ; Data Direction Register B
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IO_DDRA = $3 ; Data Direction Register A
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IO_T1CL = $4 ; Timer 1 Counter Low/High
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2023-10-26 19:51:20 +02:00
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IO_T1CH = $5
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2023-10-27 16:50:58 +02:00
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IO_T1LL = $6 ; Timer 1 Latch Low/High
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IO_T1LH = $7
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2023-10-27 16:50:58 +02:00
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IO_T2CL = $8 ; Timer 2 Counter Low/High
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2023-10-26 19:51:20 +02:00
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IO_T2CH = $9
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2023-10-27 16:50:58 +02:00
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IO_SR = $a ; Shift Register
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IO_ACR = $b ; Auxiliary Control Register
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; ACR Masks
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IO_ACR_MASK_PA = %00000001 ;
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IO_ACR_MASK_PB = %00000010 ;
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IO_ACR_MASK_SR = %00011100 ;
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IO_ACR_MASK_T2 = %00100000 ;
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IO_ACR_MASK_T1 = %11000000 ;
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; SR Modes
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IO_ACR_SR_DISABLE = %00000000 ; Disabled
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IO_ACR_SR_SIN_T2 = %00000100 ; Shift in under control of T2
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IO_ACR_SR_SIN_PHI2 = %00001000 ; Shift in under control of PHI2
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IO_ACR_SR_SIN_PHIE = %00001100 ; Shift in under control of external clock
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IO_ACR_SR_SOUT_FREE_T2 = %00010000 ; Shift out free running at T2 rate
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IO_ACR_SR_SOUT_T2 = %00010100 ; Shift out under control of T2
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IO_ACR_SR_SOUT_PHI2 = %00011000 ; Shift out under control of PHI2
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IO_ACR_SR_SOUT_PHIE = %00011100 ; Shift out under control of external clock
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; T1 Modes
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IO_ACR_T1_IRQ_LOAD = %00000000 ; Timed interrupt each time T1 is loaded
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IO_ACR_T1_IRQ_CONT = %01000000 ; Continuous interrupts
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IO_ACR_T1_IRQ_LOAD_PB7 = %10000000 ; Timed interrupt each time T1 is loaded - PB7 One Shot output
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IO_ACR_T1_IRQ_CONT_PB7 = %11000000 ; Continuous interrupts - PB7 Square wave output
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IO_PCR = $c ; Peripheral Control Register
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; PCR Masks
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IO_PCR_MASK_CA1 = %00000001 ;
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IO_PCR_MASK_CA2 = %00001110 ;
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IO_PCR_MASK_CB1 = %00010000 ;
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IO_PCR_MASK_CB2 = %11100000 ;
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; CA1 Modes
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IO_PCR_CA1_IN_AE = %00000000 ; Input-negative active edge
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IO_PCR_CA1_IP_AE = %00000001 ; Input-positive active edge
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; CA2 Modes
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IO_PCR_CA2_IN_AE = %00000000 ; Input-negative active edge
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IO_PCR_CA2_IN_AE_IRQ_IND= %00000010 ; Independent interrupt input-negative edge
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IO_PCR_CA2_IP_AE = %00000100 ; Input-positive active edge
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IO_PCR_CA2_IP_AE_IRQ_IND= %00000110 ; Independent interrupt input-positive edge
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IO_PCR_CA2_IN_HANDSHAKE = %00001000 ; Handshake output
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IO_PCR_CA2_IN_PULSE_OUT = %00001010 ; Pulse output
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IO_PCR_CA2_IN_LOW_OUT = %00001100 ; Low output
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IO_PCR_CA2_IN_HIGH_OUT = %00001110 ; High output
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; CB1 Modes
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IO_PCR_CB1_IN_AE = %00000000 ; Input-negative active edge
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IO_PCR_CB1_IP_AE = %00010000 ; Input-positive active edge
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; CB2 Modes
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IO_PCR_CB2_IN_AE = %00000000 ; Input-negative active edge
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IO_PCR_CB2_IN_AE_IRQ_IND= %00100000 ; Independent interrupt input-negative edge
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IO_PCR_CB2_IP_AE = %01000000 ; Input-positive active edge
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IO_PCR_CB2_IP_AE_IRQ_IND= %01100000 ; Independent interrupt input-positive edge
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IO_PCR_CB2_IN_HANDSHAKE = %10000000 ; Handshake output
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IO_PCR_CB2_IN_PULSE_OUT = %10100000 ; Pulse output
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IO_PCR_CB2_IN_LOW_OUT = %11000000 ; Low output
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IO_PCR_CB2_IN_HIGH_OUT = %11100000 ; High output
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IO_IFR = $d ; Interrupt Flag Register
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; IFR bits
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IO_IFR_CA2 = 0
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IO_IFR_CA1 = 1
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IO_IFR_SR = 2
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IO_IFR_CB2 = 3
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IO_IFR_CB1 = 4
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IO_IFR_T2 = 5
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IO_IFR_T1 = 6
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IO_IFR_IRQ = 7
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IO_IER = $e ; Interrupt Enable Register
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IO_RANH = $f ; no handshake
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; TODO: leave?
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2023-10-27 16:50:58 +02:00
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; .struct VIA_Pins
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; RB .byte ; $0
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; RA .byte ; $1
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; DDRB .byte ; $2
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; DDRA .byte ; $3
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; T1CL .byte ; $4
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; T1CH .byte ; $5
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; T1LL .byte ; $6
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; T1LH .byte ; $7
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; T2CL .byte ; $8
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; T2CH .byte ; $9
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; SR .byte ; $a
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; ACR .byte ; $b
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; PCR .byte ; $c
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; IFR .byte ; $d
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; IER .byte ; $e
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; RANH .byte ; $f ; no handshake
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; .endstruct
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2023-10-26 19:51:20 +02:00
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.endif
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