2023-12-23 14:18:32 +01:00
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;;********************************************************************************
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;; @module IO-W65C22
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;; @type utility
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;; @device Western Design - W65C22N Versatile Interface Adapter
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;; @details
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;;********************************************************************************
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2023-10-26 19:51:20 +02:00
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.ifndef INCLUDE_IOW65C22
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INCLUDE_IOW65C22 = 1
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2023-11-01 13:13:23 +01:00
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.scope IO
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2023-12-21 17:27:54 +01:00
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; not using a struct for this since the syntax for access would be the same,
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; ie label+IO::RA
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2023-11-01 13:13:23 +01:00
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.enum
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2023-10-26 19:51:20 +02:00
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; IO-CHIPS OFFSETS FOR PINS FROM BASE ADDRESS
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2023-11-01 13:13:23 +01:00
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RB = $0 ; Register B (ORB/IRB)
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RA = $1 ; Register A (ORA/IRA)
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DDRB = $2 ; Data Direction Register B
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DDRA = $3 ; Data Direction Register A
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T1CL = $4 ; Timer 1 Counter Low/High
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T1CH = $5
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T1LL = $6 ; Timer 1 Latch Low/High
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T1LH = $7
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T2CL = $8 ; Timer 2 Counter Low/High
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T2CH = $9
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SR = $a ; Shift Register
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ACR = $b ; Auxiliary Control Register
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PCR = $c ; Peripheral Control Register
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IFR = $d ; Interrupt Flag Register
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IER = $e ; Interrupt Enable Register
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RANH = $f ; RA without handshake
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.endenum
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.enum ACR_MASK ; ACR Masks
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PA = %00000001
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PB = %00000010
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SR = %00011100
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T2 = %00100000
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T1 = %11000000
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.endenum
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.enum ACR ; ACR Settings
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2023-10-27 16:50:58 +02:00
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; SR Modes
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2023-11-01 13:13:23 +01:00
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SR_DISABLE = %00000000 ; Disabled
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SR_SIN_T2 = %00000100 ; Shift in under control of T2
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SR_SIN_PHI2 = %00001000 ; Shift in under control of PHI2
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SR_SIN_PHIE = %00001100 ; Shift in under control of external clock
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SR_SOUT_FREE_T2 = %00010000 ; Shift out free running at T2 rate
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SR_SOUT_T2 = %00010100 ; Shift out under control of T2
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SR_SOUT_PHI2 = %00011000 ; Shift out under control of PHI2
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SR_SOUT_PHIE = %00011100 ; Shift out under control of external clock
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2023-10-27 16:50:58 +02:00
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; T1 Modes
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2023-11-01 13:13:23 +01:00
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T1_IRQ_LOAD = %00000000 ; Timed interrupt each time T1 is loaded
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T1_IRQ_CONT = %01000000 ; Continuous interrupts
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T1_IRQ_LOAD_PB7 = %10000000 ; Timed interrupt each time T1 is loaded - PB7 One Shot output
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T1_IRQ_CONT_PB7 = %11000000 ; Continuous interrupts - PB7 Square wave output
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2023-12-20 12:27:54 +01:00
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; T2 Modes
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T2_IRQ_LOAD = %00000000 ; Timed interrupt each time T2 is loaded
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T2_COUNT_PB6 = %00100000 ; Count down with pulsen on PB6
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; Latch
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LATCH_DISABLE = %00000000
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LATCH_ENBLE = %00000000
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2023-11-01 13:13:23 +01:00
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.endenum
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.enum PCR_MASK ; PCR Masks
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CA1 = %00000001 ;
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CA2 = %00001110 ;
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CB1 = %00010000 ;
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CB2 = %11100000 ;
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.endenum
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.enum PCR
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2023-10-27 16:50:58 +02:00
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; CA1 Modes
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CA1_IN_AE = %00000000 ; Input-negative active edge
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CA1_IP_AE = %00000001 ; Input-positive active edge
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2023-10-27 16:50:58 +02:00
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; CA2 Modes
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CA2_IN_AE = %00000000 ; Input-negative active edge
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CA2_IN_AE_IRQ_IND= %00000010 ; Independent interrupt input-negative edge
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CA2_IP_AE = %00000100 ; Input-positive active edge
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CA2_IP_AE_IRQ_IND= %00000110 ; Independent interrupt input-positive edge
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CA2_IN_HANDSHAKE = %00001000 ; Handshake output
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CA2_IN_PULSE_OUT = %00001010 ; Pulse output
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CA2_IN_LOW_OUT = %00001100 ; Low output
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CA2_IN_HIGH_OUT = %00001110 ; High output
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2023-10-27 16:50:58 +02:00
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; CB1 Modes
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CB1_IN_AE = %00000000 ; Input-negative active edge
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CB1_IP_AE = %00010000 ; Input-positive active edge
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2023-10-27 16:50:58 +02:00
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; CB2 Modes
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CB2_IN_AE = %00000000 ; Input-negative active edge
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CB2_IN_AE_IRQ_IND= %00100000 ; Independent interrupt input-negative edge
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CB2_IP_AE = %01000000 ; Input-positive active edge
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CB2_IP_AE_IRQ_IND= %01100000 ; Independent interrupt input-positive edge
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CB2_IN_HANDSHAKE = %10000000 ; Handshake output
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CB2_IN_PULSE_OUT = %10100000 ; Pulse output
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CB2_IN_LOW_OUT = %11000000 ; Low output
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CB2_IN_HIGH_OUT = %11100000 ; High output
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.endenum
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2023-10-27 16:50:58 +02:00
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2023-11-01 13:13:23 +01:00
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; IFR/IER bits
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.enum IRQ
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CA2 = %00000001
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CA1 = %00000010
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SR = %00000100
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CB2 = %00001000
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CB1 = %00010000
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T2 = %00100000
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T1 = %01000000
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IRQ = %10000000
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.endenum
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2023-10-26 19:51:20 +02:00
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2023-12-08 00:02:52 +01:00
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.endscope ; IO
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.endif ; guard
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